Conventionally, various comparators to be used for an A/D (analog to digital) converter or the like have been proposed (see, for example, Patent Document 1 and Non-patent Document 1). Here, a comparator having a configuration described in Non-patent Document 1 will be described below with reference to FIGS. 18, 19, 20A, 20B and 20C. FIG. 18 is a diagram showing a state of the comparator before operation (i.e., in a preparatory stage), and FIG. 19 is a diagram showing a state of the comparator during operation. Further, FIGS. 20A, 20B and 20C are graphs respectively showing temporal change of output voltages of the comparator, temporal change of output voltages in a differential preamplifier circuit section of the comparator, and temporal change of clock signals for controlling the operation of the comparator.
As shown in FIG. 18, a comparator 400 according to the prior art includes a dynamic differential preamplifier circuit section 200 arranged on an input side (a first stage), and a differential latch circuit section 300 arranged on an output side (a second stage). Incidentally, in FIG. 18, the symbols G, S and D respectively represent a gate terminal, a source terminal and a drain terminal of each MOS transistor.
The differential preamplifier circuit section 200 includes three NMOS (Negative channel Metal Oxide Semiconductor) transistors 201 to 203, and two PMOS (Positive channel Metal Oxide Semiconductor) transistors 204 and 205. Incidentally, a PMOS transistor is a MOS transistor that has a p-type channel (i.e., current path) polarity and that becomes ON state when a voltage signal of “L” state is inputted to the gate terminal thereof, so that current flows from the source terminal to the drain terminal thereof. While a NMOS transistor is a MOS transistor that has an n-type channel polarity and that becomes ON state when a voltage signal of “H” state is inputted to the gate terminal thereof, so that current flows from the drain terminal to the source terminal thereof.
The MOS transistors configuring the differential preamplifier circuit section 200 are connected with each other as shown in FIG. 18 so that each transistor performs predetermined operation. Further, the gate terminal of the NMOS transistor 201 and the gate terminal of the NMOS transistor 202 are connected to an input terminal 206 and an input terminal 207 respectively. The gate terminal of the NMOS transistor 203 and the gate terminals of the two PMOS transistors 204 and 205 are connected to a clock terminal 208 to which a clock signal CLK is inputted. Further, the source terminals of the PMOS transistor 204 and 205 are connected to a power supply terminal 310 of a power supply voltage Vs. In other words, the operation of the differential preamplifier circuit section 200 is controlled by the clock signal inputted to the gate terminals of the NMOS transistor 203, the PMOS transistor 204 and the PMOS transistor 205.
The differential latch circuit section 300 includes four NMOS transistors 301 to 304, and three PMOS transistors 305 to 307. These MOS transistors in the differential latch circuit section 300 are connected with each other as shown in FIG. 18 so that each transistor performs predetermined operation.
Further, the gate terminal of the PMOS transistor 307 in the differential latch circuit section 300 is connected to a clock terminal 311 to which a clock signal with opposite phase to the clock signal CLK inputted to the differential preamplifier circuit section 200 (i.e., to the clock terminal 208) is inputted. The operation of the PMOS transistor 307 is controlled by the clock signal with opposite phase. In other words, the operation of the latch circuit, which is configured by two NMOS transistors 301 and 302 and two PMOS transistors 305 and 306, is controlled by performing an on-off control on the PMOS transistor 307 by the clock signal with opposite phase. Further, the source terminals of the PMOS transistor 307 is connected to the power supply terminal 310 of the power supply voltage Vs.
Further, the gate terminals of the NMOS transistor 303 and the NMOS transistor 304 in the differential latch circuit section 300 are respectively connected to output terminals (nodes) N1 and N2 of the differential preamplifier circuit section 200. The NMOS transistors 303 and 304 are on-off controlled by the output signal from the differential preamplifier circuit section 200, so that the current flowing through the latch circuit is controlled. In other words, the operation of the differential latch circuit section 300 is controlled by the clock signal inputted to the gate terminal of the PMOS transistor 307 and the output voltage signals inputted from the differential preamplifier circuit section 200 to the NMOS transistors 303 and 304.
Next, the operation of the comparator 400 according to the prior art will be described below in more detail with reference to FIGS. 18, 19, 20A, 20B and 20C.
As shown in FIG. 18, in the preparatory stage (referred to as “state 1” hereinafter) of the operation, a clock voltage of “L (Low)” state and a clock voltage of “H (High)” state are respectively inputted to the clock terminals 208 and 311 of the comparator 400. In such a case, in the differential preamplifier circuit section 200, the two PMOS transistors 204 and 205 become ON state, and the NMOS transistor 203 becomes OFF state. At this time, since the NMOS transistor 203 is in OFF state, no through-current flows through the differential preamplifier circuit section 200; however, since the PMOS transistors 204 and 205 are in ON state, the voltage at the nodes N1 and N2 in the differential preamplifier circuit section 200 will increase due to the power supply voltage Vs. As a result, the voltages Vg1 and Vg2 respectively outputted from the nodes N1 and N2 in the differential preamplifier circuit section 200 will both become “H” state.
On the other hand, in state 1, since the clock voltage of “H” state is inputted to the gate terminal of the PMOS transistor 307 in the differential latch circuit section 300, the PMOS transistor 307 becomes OFF state. In such a case, no current flows from the side of the power supply voltage Vs to the latch circuit, which is configured by two NMOS transistors 301 and 302 and two PMOS transistors 305 and 306. Further, in state 1, since the gate voltages (Vg1 and Vg2) of the NMOS transistors 303 and 304 in the differential latch circuit section 300 are in “H” state, the two transistors both become ON state. Thus, nodes N3 and N4 in the differential latch circuit section 300 become the same potential as the ground (i.e., become zero potential). As a result, voltages Vo1 and Vo2 outputted respectively from output terminals 312 and 313 of the comparator 400 both become “L” state.
Incidentally, in characteristics shown in FIGS. 20A to 20C, the characteristic before time t1 indicates the change of the output voltages Vo1 and Vo2 of the comparator 400, the change of the output voltages Vg1 and Vg2 of the differential preamplifier circuit section 200, and the change of the clock voltages inputted to the clock terminals 208 and 311 in state 1. However, in the characteristics shown in FIGS. 20A to 20C, the state “H” corresponds to 1 [V], and the “L” state corresponds to 0 [V].
Next, a state of the comparator 400 during operation (referred to as “state 2” hereinafter) will be described below with reference to FIG. 19. However, the example shown in FIG. 19 is based on a case where the voltage Vi1 inputted to one input terminal 206 of the comparator 400 is higher than the voltage Vi2 inputted to the other input terminal 207 of the comparator 400 (i.e., Vi1>Vi2).
In state 2, the clock voltage inputted to the clock terminal 208 changes to “H” state. Thus, in the differential preamplifier circuit section 200, the two PMOS transistors 204 and 205 become OFF state, and the NMOS transistor 203 becomes ON state. Since the voltage values of the nodes N1 and N2 in the differential preamplifier circuit section 200 was in “H” state in state 1 (i.e., the preparatory stage), when the NMOS transistor 203 becomes ON state in state 2, current will flow to the ground through the NMOS transistors 201 to 203. Thus, the voltage values of the nodes N1 and N2 will decrease with elapse of time and transit to “L” state.
However, at this time, currents corresponding to the input voltages Vi1 and Vi2 applied to the gate terminals of the NMOS transistors 201 and 202 will flow through the NMOS transistors 201 and 202. In the example shown in FIG. 19, since Vi1>Vi2, the current flowing through the NMOS transistor 201 is larger than the current flowing through the NMOS transistor 202. As a result, the voltage drop rate of the output voltage Vg1 at the node N1 with respect to the time is larger than the voltage drop rate of the output voltage Vg2 at the node N2 with respect to the time.
Such circumstance is shown in FIG. 20B. After the state of the comparator 400 is switched to state 2 (i.e., after time t1), the output voltage Vg1 at the node N1 transits to “L” state more early than the output voltage Vg2 at the node N2. Thus, during the period between the time when the state of the comparator is switched to state 2 and the time when the output voltage Vg2 at the node N2 transits to the “L” state, the output voltage Vg2 at the node N2 is higher than the output voltage Vg1 at the node N1. In other words, during the transition period of the output voltage Vg2 at the node N2, the gate voltage of the NMOS transistor 304 is higher than the gate voltage of the NMOS transistor 303 in the differential latch circuit section 300.
Further, when the state of the comparator becomes state 2, the clock voltage inputted to the clock terminal 311 is changed to the “L” state, and the PMOS transistor 307 in the differential latch circuit section 300 becomes ON state. Thus, current begins to flow through the latch circuit, which is configured by two NMOS transistors 301 and 302 and two PMOS transistors 305 and 306. However, as described above, since the gate voltage of the NMOS transistor 304 is higher than the gate voltage of the NMOS transistor 303 during the transition period of the output voltage Vg2 at the node N2, the potential (Vo1) at the node N3 is slightly higher than the potential (Vo2) at the node N4.
Such circumstance is shown in FIG. 20A. After the comparator is switched to state 2 (i.e., after time t1), both the output voltage Vo1 (solid line) at the node N3 and the output voltage Vo2 (broken line) at the node N4 increase with elapse of time; however, the output voltage Vo1 begins to become higher than the output voltage Vo2 near time t2. Thus, positive feedback operates in the latch circuit, which is configured by two NMOS transistors 301 and 302 and two PMOS transistors 305 and 306 (the details of the positive feedback operation will be described later in the description of the best modes of the present invention). As a result, as shown in FIG. 20A, after time t2, the output voltage Vo1 at the node N3 continues to increase and is finally fixed in “H” state. On the other hand, the output voltage Vo2 at the node N4 continues to decrease and is finally fixed in “L” state. Thus, the comparison state (i.e., the comparison result) of the input voltages Vi1 and Vi2 is kept in the differential latch circuit section 300 and outputted from the output terminals 312 and 313.
Further, at this time, the PMOS transistor 305 of the latch circuit is in ON state, and the NMOS transistor 301 of the latch circuit is in OFF state (see FIG. 19), wherein the gate terminal of the PMOS transistor 305 and the gate terminal of the NMOS transistor 301 are connected to the node N4. On the other hand, the PMOS transistor 306 of the latch circuit is in OFF state, and the NMOS transistor 302 of the latch circuit is in ON state (see FIG. 19), wherein the gate terminal of both the PMOS transistor 306 and the gate terminal of the NMOS transistor 302 are connected to the node N3. Further, since the gate voltages (Vg1 and Vg2) applied to two NMOS transistors 303 and 304 are in state, the NMOS transistors 303 and 304 are in OFF state. Thus, no steady current (through-current) flows in the differential latch circuit section 300. The comparator 400 according to the prior art operates in the aforesaid manner.